Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device including buried bit lines, and a method for fabricating the semiconductor device.
To increase the integration degree, memory devices manufactured by under 40 nm process are useful. In case of planar transistors or recessed gate transistors used in cell architectures of 8F2 or 6F2, where F denotes a minimum feature size, it is difficult to perform scaling under 40 nm. Therefore, a cell having a cell architecture of 4F2 that may improve the integration degree by 1.5 to 2 times with the same scaling is useful. Accordingly, a vertical gate forming process is introduced.
Vertical gate forming process is a process for forming a surround-type gate electrode, which is referred to as a vertical gate, hereafter, surrounding an active pillar extended vertically from a semiconductor substrate and forming a source region and a drain region in the upper and lower portions of the active pillar with respect to the vertical gate, respectively. With the vertical gate forming process, channels are formed vertically and accordingly, although the area of a transistor on the semiconductor substrate is reduced, the length of channels is not restricted by the reduced area.
Through the vertical gate forming process, memory cells come to have buried bit lines for high integration, which are formed by performing ion implantation using a dopant.
However, in shrinking a semiconductor device, reducing the resistance of the buried bit lines by performing the dopant ion implantation is difficult. Thus, the characteristics of the semiconductor device may deteriorate.
To alleviate such a concern, a metal silicidation method is suggested for forming buried bit lines.
The conventional technology, however, has the following drawbacks.
According to the metal silicidation method, a silicided portion is cut according to the size of each cell after the metal silicidation in order to separate neighboring bit lines from each other. When the silicided portion is cut, the cross-sectional area of a contact is reduced and the reduced cross-sectional area increases a resistance value. Also, since the metal silicidation is performed from the surface of the space between active pillars, the distance from the vertical gate becomes short and thus bridging may occur.
According to conventional methods, active pillars are formed first and then bit lines are formed later. The formation of bit lines after the formation of the active pillars may negatively affect resistance.
Therefore, it is required to develop a method that can resolve the problems of complicated fabrication process and resistance increasing due, to the reduced cross-sectional area when the bit lines are formed, while using the vertical gate forming process.